View AD826ARZ_4553294.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad826 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., high-speed, low-power dual operational amplifier connection diagram 8-lead plastic mini-dip and so package 1 2 3 4 8 7 6 5 ad826 v+ out2 ?n2 +in2 out1 ?n1 +in1 v the ad826 features high output current drive capability of 50 ma min per amp, and is able to drive unlimited capacitive loads. with a low power supply current of 15 ma max for both amplifiers, the ad826 is a true general purpose operational amplifier. the ad826 is ideal for power sensitive applications such as video cameras and portable instrumentation. the ad826 can operate from a single +5 v supply, while still achieving 25 mhz of band- width. furthermore the ad826 is fully specified from a single +5 v to 15 v power supplies. the ad826 excels as an adc/dac buffer or active filter in data acquisition systems and achieves a settling time of 70 ns to 0.01%, with a low input offset voltage of 2 mv max. the ad826 is available in small 8-lead plastic mini-dip and so packages. 10 90 100 0% 500ns 5v 5v c l = 100pf c l = 1000pf features high speed: 50 mhz unity gain bandwidth 350 v/ s slew rate 70 ns settling time to 0.01% low power: 7.5 ma max power supply current per amp easy to use: drives unlimited capacitive loads 50 ma min output current per amplifier specified for +5 v, 5 v and 15 v operation 2.0 v p-p output swing into a 150 load (v s = +5 v) good video performance differential gain & phase error of 0.07% & 0.11 excellent dc performance: 2.0 mv max input offset voltage applications unity gain adc/dac buffer cable drivers 8- and 10-bit data acquisition systems video line driver active filters product description the ad826 is a dual, high speed voltage feedback op amp. it is ideal for use in applications which require unity gain stability and high output drive capability, such as buffering and cable driving. the 50 mhz bandwidth and 350 v/ s slew rate make the ad826 useful in many high speed applications including: video, catv, copiers, lcds, image scanners and fax machines. tektronix p6201 fet probe hp pulse generator 1/2 ad826 1k 50 1k c l v out v in tektronix 7a24 fet preamp v s 0.01f 3.3f 0.01f v s 3.3f 1 3 2 driving a large capacitive load rev. c
C2C ad826?pecifications (@ t a = +25 c, unless otherwise noted) parameter conditions v s min typ max unit dynamic performance unity gain bandwidth 5 v 30 35 mhz 15 v 45 50 mhz 0, +5 v 25 29 mhz bandwidth for 0.1 db flatness gain = +1 5 v 10 20 mhz 15 v 25 55 mhz 0, +5 v 10 20 mhz full power bandwidth 1 v out = 5 v p-p r load = 500 ? 5 v 15.9 mhz v out = 20 v p-p r load = 1 k ? 15 v 5.6 mhz slew rate r load = 1 k ? 5 v 200 250 v/ s gain = ? 15 v 300 350 v/ s 0, +5 v 150 200 v/ s settling time to 0.1% ?.5 v to +2.5 v 5 v 45 ns 0 v?0 v step, a v = ? 15 v 45 ns to 0.01% ?.5 v to +2.5 v 5 v 70 ns 0 v?0 v step, a v = ? 15 v 70 ns noise/harmonic performance total harmonic distortion f c = 1 mhz 15 v ?8 db input voltage noise f = 10 khz 5 v, 15 v 15 nv/ hz input current noise f = 10 khz 5 v, 15 v 1.5 pa/ hz differential gain error ntsc 15 v 0.07 0.1 % (r1 = 150 ? ) gain = +2 5 v 0.12 0.15 % 0, +5 v 0.15 % differential phase error ntsc 15 v 0.11 0.15 degrees (r1 = 150 ? ) gain = +2 5 v 0.12 0.15 degrees 0, +5 v 0.15 degrees dc performance input offset voltage 5 v to 15 v 0.5 2 mv t min to t max 3mv offset drift 10 v/ c input bias current 5 v, 15 v 3.3 6.6 a t min 10 a t max 4.4 a input offset current 5 v, 15 v 25 300 na t min to t max 500 na offset current drift 0.3 na/ c open-loop gain v out = 2.5 v 5 v r load = 500 ? 2 4 v/mv t min to t max 1.5 v/mv r load = 150 ? 1.5 3 v/mv v out = 10 v 15 v r load = 1 k ? 3.5 6 v/mv t min to t max 2 5 v/mv v out = 7.5 v 15 v r load = 150 ? (50 ma output) 2 4 v/mv input characteristics input resistance 300 k ? input capacitance 1.5 pf input common-mode voltage range 5 v +3.8 +4.3 v ?.7 ?.4 v 15 v +13 +14.3 v ?2 ?3.4 v 0, +5 v +3.8 +4.3 v +1.2 +0.9 v common-mode rejection ratio v cm = 2.5 v, t min ? max 5 v 80 100 db v cm = 12 v 15 v 86 120 db t min to t max 15 v 80 100 db rev. c
C3C ad826 absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . see derating curves small outline (r) . . . . . . . . . . . . . . . . see derating curves input voltage (common mode) . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 6 v output short circuit duration . . . . . . . see derating curves storage temperature range (n, r) . . . . . . . ?5 c to +125 c operating temperature range . . . . . . . . . . 40 c to +85 c lead temperature range (soldering 10 seconds) . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . 2 specification is for device in free air: 8-lead plastic package, ja = 100 c/watt; 8-lead soic package, ja = 155 c/watt. parameter conditions v s min typ max unit output characteristics output voltage swing r load = 500 ? 5 v 3.3 3.8 v r load = 150 ? 5 v 3.2 3.6 v r load = 1 k ? 15 v 13.3 13.7 v r load = 500 ? 15 v 12.8 13.4 v r load = 500 ? 0, +5 v +1.5, +3.5 v output current 15 v 50 ma 5 v 50 ma 0, +5 v 30 ma short-circuit current 15 v 90 ma output resistance open loop 8 ? matching characteristics dynamic crosstalk f = 5 mhz 15 v ?0 db gain flatness match g = +1, f = 40 mhz 15 v 0.2 db slew rate match g = ? 15 v 10 v/ s dc input offset voltage match t min ? max 5 v to 15 v 0.5 2 mv input bias current match t min ? max 5 v to 15 v 0.06 0.8 a open-loop gain match v o = 10 v, r load = 1 k ? , t min ? max 15 v 0.15 0.01 mv/v common-mode rejection ratio match v cm = 12 v, t min ? max 15 v 80 100 db power supply rejection ratio match 5 v to 15 v, t min ? max 80 100 db power supply operating range dual supply 2.5 18 v single supply +5 +36 v quiescent current/amplifier 5 v 6.6 7.5 ma t min to t max 5 v 7.5 ma 15 v 7.5 ma t min to t max 15 v 6.8 7.5 ma power supply rejection ratio v s = 5 v to 15 v, t min to t max 75 86 db notes 1 full power bandwidth = slew rate/2 v peak . specifications subject to change without notice. esd susceptibility esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. although the ad826 features proprietary esd protection cir- cuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid any performance degradation or loss of functionality. 2.0 0 50 90 1.5 0.5 30 1.0 50 70 30 10 10 80 40 40 60 20 0 20 ambient temperature c maximum power dissipation watts 8-lead mini-dip package 8-lead soic package t j = +150 c maximum power dissipation vs. temperature for different package types rev. c
ad826 C4C 20 0 02 0 15 5 5 10 10 15 input common-mode range volts supply voltage volts v cm +v cm figure 1. common-mode voltage range vs. supply 20 0 020 15 5 5 10 10 15 supply voltage volts output voltage swing volts r l = 150v r l = 500v figure 2. output voltage swing vs. supply 30 0 10k 15 5 100 10 10 20 1k 25 load resistance output voltage swing volts p-p v s = 15v v s = 5v figure 3. output voltage swing vs. load resistance 40 c 7.7 5.7 020 7.2 6.2 5 6.7 10 15 supply voltage volts quiescent supply current per amp ma +25 c +85 c figure 4. quiescent supply current per amp vs. supply voltage for various temperatures slew rate v/s 20 5 015 10 supply voltage volts 200 300 350 400 250 figure 5. slew rate vs. supply voltage 100 1 0.01 1k 10k 100m 10m 1m 100k 0.1 10 frequency hz closed-loop output impedance figure 6. closed-loop output impedance vs. frequency ?typical characteristics rev. c
ad826 C5C 7 1 140 4 2 40 3 60 6 5 120 806040 100 20 0 20 temperature c input bias current a figure 7. input bias current vs. temperature 130 30 140 90 50 40 70 60 110 12010080604020 0 20 temperature c short circuit current ma sink current source current figure 8. short circuit current vs. temperature 100 20 60 140 80 40 40 60 100 120 80604020 0 20 temperature c phase margin degrees 20 80 40 60 unity gain bandwidth mhz phase margin gain bandwidth figure 9. unity gain bandwidth and phase margin vs. temperature 100 20 1g 40 0 10k 20 1k 80 60 100m 10m 1m 100k frequency hz +100 +40 0 +20 +80 +60 phase margin degrees open-loop gain db gain 15v supplies gain 5v supplies phase 5v or 15v supplies rl = 1k figure 10. open-loop gain and phase margin vs. frequency 4 1 100 1k 10k 2 3 5 6 load resistance open-loop gain v/mv 15v 5v 7 figure 11. open-loop gain vs. load resistance 100 10 100m 30 20 1k 100 40 50 60 70 80 90 10m 1m 100k 10k frequency hz psr db positive supply negative supply figure 12. power supply rejection vs. frequency rev. c
ad826 C6C 140 60 1k 10m 120 80 10k 100 100k 1m frequency hz cmr db figure 13. common-mode rejection vs. frequency 30 10 0 100k 1m 100m 10m 20 frequency hz output voltage volts p-p r l = 150 r l = 1k figure 14. large signal frequency response 10 10 160 4 8 20 6 0 2 2 0 4 6 8 140 120 100 806040 settling time ns output swing from 0 to v 0.01% 0.1% 1% 1% 0.01% 0.1% figure 15. output swing and error vs. settling time 40 100 10m 70 90 1k 80 100 50 60 1m 100k 10k frequency hz harmonic distortion db v in = 1v p-p gain = +2 2 nd harmonic 3 rd harmonic figure 16. harmonic distortion vs. frequency 50 0 10m 30 10 10 20 3 40 1m 100k 10k 1k 100 frequency hz input voltage noise nv/ hz figure 17. input voltage noise spectral density 380 300 60 140 360 320 40 340 100 120 80604020 0 20 temperature c slew rate v/s figure 18. slew rate vs. temperature rev. c
ad826 C7C frequency hz gain db 5 0 5 100k 1m 100m 10m 1 2 3 4 1 2 3 4 v s 15v 5v 5v 0.1db flatness 55mhz 20mhz 20mhz v out v in 781 150 v s = 15v v s = 5v v s = 5v figure 19. closed-loop gain vs. frequency supply voltage volts 0.13 0.07 0.10 differential phase degrees differential gain percent 0.10 15 0.13 0.11 0.12 5 10 diff gain diff phase figure 20. differential gain and phase vs. supply voltage 30 70 110 100k 100m 10m 1m 10k 90 50 60 80 100 40 frequency hz crosstalk db 15v r l = 1k 5v r l = 150 figure 21. crosstalk vs. frequency frequency hz 5 0 5 100k 1m 100m 10m 1 2 3 4 1 2 3 4 0.1db v s c c flatness 15v 3pf 16mhz 5v 4pf 14mhz 5v 6pf 12mhz 1k 1k v in c c v out gain db v s = 15v v s = 5v v s = 5v figure 22. closed-loop gain vs. frequency, gain = C1 frequency hz gain db 1.0 0 1.0 100k 1m 100m 10m 0.2 0.4 0.6 0.8 0.2 0.4 0.6 0.8 v s = 15v v s = 5v v s = +5v figure 23. gain flatness matching vs. supply, g = +1 1/2 ad826 3 2 1 use ground plane pinout shown is for minidip package v in v s 8 r l = 150 for v s = 5v, 1k for v s = 15v r l 1f 0.1f 1/2 ad826 5 6 7 4 r l v s 1f 0.1f v out figure 24. crosstalk test circuit rev. c
ad826 C8C tektronix p6201 fet probe pulse (ls) or function (ss) generator 1/2 ad826 r in 100 50 1k r l v out v in tektronix 7a24 preamp v s 0.01f 3.3f 0.01f v s 3.3f figure 25. noninverting amplifier configuration 10 90 100 0% 50ns 5v 5v figure 26. noninverting large signal pulse response, r l = 1 k ? 10 90 100 0% 50ns 5v 5v figure 27. noninverting large signal pulse response, r l = 150 ? 10 90 100 0% 50ns 200mv 200mv figure 28. noninverting small signal pulse response, r l = 1 k ? 5v 10 90 100 0% 50ns 200mv 200mv figure 29. noninverting small signal pulse response, r l = 150 ? rev. c
ad826 C9C v s tektronix p6201 fet probe pulse (ls) or function (ss) generator 1/2 ad826 1k 0.01 f r l v out tektronix 7a24 preamp r in 1k 50 v in 3.3 f 0.01f v s 3.3f figure 30. inverting amplifier configuration 10 90 100 0% 5v 50ns 5v figure 31. inverting large signal pulse response, r l = 1 k ? 10 90 100 0% 5v 50ns 5v figure 32. inverting large signal pulse response, r l = 150 ? 10 90 100 0% 200mv 50ns 200mv figure 33. inverting small signal pulse response, r l = 1 k ? 10 90 100 0% 200mv 50ns 200mv figure 34. inverting small signal pulse response, r l = 150 ? rev. c
ad826 -10- rev. c theory of operation the ad826 is a low cost, wide band, high performance dual operational amplifier which can drive heavy capacitive and resistive loads. it also achieves a constant slew rate, bandwidth and settling time over its entire specified temperature range. the ad826 (figure 35) consists of a degenerated npn differential pair driving matched pnps in a folded-cascode gain stage. the output buffer stage employs emitter followers in a class ab amplifier which delivers the necessary current to the load while maintaining low levels of distortion. output c f null1 null8 ?v s ?in +in + v s figure 35. simplified schematic the capacitor, c f , in the output stage mitigates the effect of capacitive loads. with low capacitive loads, the gain from the compensation node to the output is very close to unity. in this case, c f is bootstrapped and does not contribute to the overall compensation capacitance of the device. as the capacitive load is increased, a pole is formed with the output impedance of the output stage. this reduces the gain, and therefore, c f is incompletely bootstrapped. effectively, some fraction of c f contributes to the overall compensation capacitance, reducing the unity gain bandwidth. as the load capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier. input considerations an input protection resistor (r in in figure 25) is required in circuits where the input to the ad826 will be subjected to transient or continuous overload voltages exceeding the 6 v maximum differential limit. this resistor provides protection for the input transistors by limiting their maximum base current. for high performance circuits, it is recommended that a balancing resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. the balancing resistor equals the parallel combination of r in and r f and thus provides a matched impedance at each input terminal. the offset voltage error will then be reduced by more than an order of magnitude. applying the ad826 the ad826 is a breakthrough dual amp that delivers precision and speed at low cost with low power consumption. the ad826 offers excellent static and dynamic matching characteristics, combined with the ability to drive heavy resistive and capacitive loads. as with all high frequency circuits, care should be taken to maintain overall device performance as well as their matching. the following items are presented as general design considerations. circuit board layout input and output runs should be laid out so as to physically isolate them from remaining runs. in addition, the feedback resistor of each amplifier should be placed away from the feedback resistor of the other amplifier, since this greatly reduces inter-amp coupling. choosing feedback and gain resistors in order to prevent the stray capacitance present at each amplifiers summing junction from limiting its performance, the feedback resistors should be 1 k. since the summing junction capacitance may cause peaking, a small capacitor (1 pfC5pf) maybe paralleled with r f to neutralize this effect. finally, sockets should be avoided, because of their tendency to increase interlead capacitance. power supply considerations to ensure the proper operation of the ad826, connect the positive supply before the negative supply. also, proper power supply decoupling is critical to preserve the integrity of high frequency signals. in carefully laid out designs, decoupling capacitors should be placed in close proximity to the supply pins, while their lead lengths should be kept to a minimum. these measures greatly reduce undesired inductive effects on the amplifiers response. though two 0.1 f capacitors will typically be effective in decoupling the supplies, several capacitors of different values can be paralleled to cover a wider frequency range.
ad826 C11C single supply operation an exciting feature of the ad826 is its ability to perform well in a single supply configuration (see figure 37). the ad826 is ideally suited for applications that require low power dissipation and high output current and those which need to drive large capacitive loads, such as high speed buffering and instrumentation. referring to figure 36, careful consideration should be given to the proper selection of component values. the choices for this particular circuit are: (r1 + r3) r2 combine with c1 to form a low frequency corner of approximately 30 hz. v s 1/2 ad826 r2 10k 3.3f 0.01f c3 0.1f v out r1 9k r3 1k c2 0.1f v in c1 1f c l 200pf r l 150 c out figure 36. single supply amplifier configuration r3 and c2 reduce the effect of the power supply changes on the output by low-pass filtering with a corner at 1 2 r 3 c 2 . the values for r l and c l were chosen to demonstrate the ad826 s exceptional output drive capability. in this configura- tion, the output is centered around 2.5 v. in order to eliminate the static dc current associated with this level, c3 was inserted in series with r l . 10 90 100 0% 500mv 100ns 500mv figure 37. single supply pulse response, g = +1, r l = 150 ? , c l = 200 pf parallel amps provide 100 ma to load by taking advantage of the superior matching characteristics of the ad826, enhanced performance can easily be achieved by employing the circuit in figure 38. here, two identical cells are paralleled to obtain even higher load driving capability than that of a single amplifier (100 ma min guaranteed). r1 and r2 are included to limit current flow between amplifier outputs that would arise in the presence of any residual mismatch. v s v in v out 1k r1 5 r2 5 v s 1k 1k 1k r l 1/2 ad826 1/2 ad826 0.1f 1f 0.1f 1f figure 38. parallel amp configuration rev. c
ad826 C12C single-ended to differential line driver outstanding cmrr (> 80 db @ 5 mhz), high bandwidth, wide supply voltage range, and the ability to drive heavy loads, make the ad826 an ideal choice for many line driving applications. in this application, the ad830 high speed video difference amp serves as the differential line receiver on the end of a back terminated, 50 ft., twisted-pair transmission line (see figure 40). the overall system is configured in a gain of +1 and has a 3 db bandwidth of 14 mhz. figure 39 is the pulse response with a 2 v p-p, 1 mhz signal input. 10 90 100 0% 2v 200ns 2v figure 39. pulse response 15v 1/2 ad826 0.01f 2.2f 1/2 ad826 36 1.05k 5pf bnc i n 15v ad830 v out 50 feet twisted pair z = 72 36 0.1f 1.05k 5pf 1.05k 1.05k 0.1f 0.01f 2.2f 36 36 15v 0.01f 0.1f 15v 0.1f 0.01f figure 40. differential line driver low distortion line driver the ad826 can quickly be turned into a powerful, low distor- tion line driver (see figure 41). in this arrangement the ad826 can comfortably drive a 75 ? back-terminated cable, with a 5 mhz, 2 v p-p input; all of this while achieving the harmonic distortion performance outlined in the following table. configuration 2nd harmonic 1. no load 78.5 dbm 2. 150 ? r l only 63.8 dbm 3. 150 ? r l 7.5 ? r c 70.4 dbm in this application one half of the ad826 operates at a gain of 2.1 and supplies the current to the load, while the other pro- vides the overall system gain of 2. this is important for two reasons: the first is to keep the bandwidth of both amplifiers the same, and the second is to preserve the ad826 s ability to oper- ate from low supply voltages. r c varies with the load and must be chosen to satisfy the following equation: r c = mr l where m is defined by [(m+ 1) g s = g d ] and g d = driver s gain, g s = system gain. 1.1k 1k 1k r l 1/2 ad826 1/2 ad826 r c 7.5 1k 75 75 75 v s 1f 0.1f 0.1f 1f figure 41. low distortion amplifier rev. c
ad826 C13C high performance adc buffer figure 42 is a schematic of a 12-bit high speed analog-to-digital converter. the ad826 dual op amp takes a single ended input and drives the ad872 a/d converter differentially, thus reduc- ing 2nd harmonic distortion. figure 43 is a fft of a 1 mhz input, sampled at 10 mhz with a thd of 78 db. the ad826 can be used to amplify low level signals so that the entire range of the converter is used. the ability of the ad826 to perform on a 5 volt supply or even with a single 5 volts combined with its rapid settling time and ability to deliver high current to compli- cated loads make it a very good flash a/d converter buffer as well as a very useful general purpose building block. v s 1/2 ad826 52.5 0.1f 1k 1k 1k 1k ad872 12-bit 10msps adc v ina v inb 50 coax cable v in 500mv p-p max common 100f 25v 1/2 ad826 v s 0.1f 100f 25v v s v s 5v 5v figure 42. a differential input buffer for high bandwidth adcs figure 43. fft, buffered a/d converter rev. c
ad826 -14- rev. c outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 44. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 45. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ad826an ?40c to +85c 8-lead pdip n-8 ad826anz ?40c to +85c 8-lead pdip n-8 ad826ar ?40c to +85c 8-lead soic _ nr - 8 ad826ar-reel ?40c to +85c 8-lead soic _ nr - 8 ad826ar-reel7 ?40c to +85c 8-lead soic _ nr - 8 AD826ARZ ?40c to +85c 8-lead soic _ nr - 8 AD826ARZ-reel ?40c to +85c 8-lead soic _ nr - 8 AD826ARZ-reel7 ?40c to +85c 8-lead soic _ nr - 8 1 z = rohs compliant part.
ad826 rev. c -15- revision history changed power supply bypassing section to power supply considerations section ................................................................... 10 changes to power supply considerations section .................... 10 updated outline dimensions ........................................................ 14 changes to ordering guide ........................................................... 14 ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08950-0-4/10(c)

▲Up To Search▲

Price & Availability of AD826ARZ

	To Download AD826ARZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .